In recent years, DRAMs have made a significant advance in terms of circuit integration and a 1 Gb DRAM development chip has already been made public. The biggest challenge faced in realizing such large capacity DRAMs is an increase in power consumption. The power consumption of DRAMs includes the power consumption by memory arrays and peripheral circuits. Normally, the former accounts for the major portion of the DRAM's power consumption. The power consumed by the memory arrays is due to the parasitic capacitors Cd of data lines that are charged or discharged. As the capacity of memory arrays increases, the number of data lines charged and discharged simultaneously increases, thus increasing the power consumption of the memory arrays.
Finding a method of hierarchically structuring the data lines and dividing them into multiple parts to reduce the Cd charge/discharge power or to increase the number of readout signals from memory cells is drawing increased attention. A method of keeping the chip area from increasing when the number of divisions of data lines is increased is detailed as a BMGB (bidirectional matched global bit line) method in an IEEE publication entitled "1993 Symposium on VLSI Circuits Digest of Technical Papers", pp. 91-92 (1993).
FIG. 16 shows a memory array of the BMGB method described in FIG. 1(b) of the above-mentioned publication. Memory cells (MC's) are connected to the intersections between the word lines (W) and the data lines (D) and have a cell arrangement that is of a folded data line structure. At each data line D, there is provided a data line connection switch (QT). A global data line pair (GD-GDB) is provided parallel to data lines D. Three global data line pairs (GD0-GD0B to GD2-GD2B) are aligned in the direction of data lines and are connected with each other by global data line separation switches (QM0, QM0B, QM1 and QM1B). The global data line pairs are connected to the sense amplifiers (SA0, SA1) at both ends as shown.
The connection relation between the data lines D and the global data lines GD is as follows. The pairs D0-D0B and D1-D1B are connected at their right ends to QT0 and QT1, which in turn are connected to GD0-GD0B and GD1-GD1B, respectively. D2-D2B and D3-D3B are connected at their left ends to QT2 and QT3, which in turn are connected to GD1-GD1B and GD0-GD0B, respectively. That is, in this example, data line connection switches (QTs) and global data line separation switches (QMs) are concentrated in the switch block SWB. Other data lines are similarly connected to global data lines.
FIG. 16 shows the switch control when reading data from memory cells (MC) at the intersections between W0 and D0 and D1. Only QT0 and QT1 are turned on, with other data line connection switches (QT) turned off. QM0-QM0B are turned off, with QM1-QM1B turned on. This connects D0-D0B to SA0 through GD0-GD0B, and D1-D1B to SA1 through GD1-GD1B and GD2-GD2B.
This method reduces the length of data lines connected to the sense amplifiers to 1/4 compared to that of the normal array configuration and also reduces the parasitic capacitance Cd to 1/4. On the other hand, this configuration connects extra parasitic capacitance of global data lines. Data lines have a large number of memory cell transistors connected thereto and thus have a large parasitic capacitance whereas global data lines have a simple wiring configuration using a wiring layer located above that of data lines and have a relatively small parasitic capacitance. Hence, the total parasitic capacitance connected to the sense amplifiers is smaller than the parasitic capacitance of the conventional method. This allows reduction in the charge/discharge power consumption of the array and an improved signal to noise (S/N) ratio.
FIG. 23 shows conventional twisted global data lines according to FIG. 2 of the above-mentioned IEEE publication, in which the global data lines are twisted to reduce coupling noise between global data lines. In the figure, the present inventors assumed that the length of global data lines corresponds to 1024 word lines and the length of data lines to 128 word lines. The sense amplifier blocks (SB) include CMOS sense amplifiers. Data lines and data line connection switches are not shown.
As shown in the figure, global data lines connected to SB0 and SB1 are twisted in an area between QM0 and QM2, and global data lines connected to SB2 and SB3 are twisted in an area between QM6 and QM8, shifted one column from the first area. Other global data lines are arranged by repeating the configuration of FIG. 23 as a unit in the direction of word lines.
The following is a discussion of the problems in the prior art as discovered by the present inventors:
(1) The first problem is related to the area needed for the switch. FIG. 17 shows a plan view (example layout) of a concrete integrated circuit that realizes the switch block SWB of the BMGB system of FIG. 16. It is assumed that switches QT and QM can each be realized by a single MOS transistor. In the figure, ACT represents an active region where MOS transistors are formed; FG a gate electrode; CONT a connection region (through-hole region) where a conductive layer forming data lines and ACT are connected; and TC1 a connection region where a conductive layer forming data lines and a conductive layer forming global data lines are connected. In the layout of FIG. 17, an ideal layout rule is assumed in which the minimum fabrication dimension is represented by F and the lithography deviation between layers is zero. This layout rule allows the switch portion of the array of FIG. 16 to be formed in an area 8 F long in the word line direction and 13 F long in the data line direction, the total length of the switch portion being 26 F. This layout, however, has a problem that there are many intersections of wires, making the layout difficult to form and increasing the area. Further, it is necessary in forming wiring to use narrow diffusion layers at intersections, thus increasing resistance of the switch portion. PA1 (2) The second problem is one of signal delay and power consumption when global data lines become long. In the array of FIG. 16, when the chip increases in capacity and the array size becomes large, the global data line becomes long, giving rise to a problem of signal delay and increased power consumption at the global data line. PA1 (3) The third problem has to with the signal to noise (S/N) ratio when the global data line becomes long. The imbalance in the length of the global data lines (GD) connected to SA0 and SA1 deteriorates the S/N. For example, in FIG. 16, when a word line W0 is selected, the data line pair D0-D0B is connected to SA0 through a GD0-GD0B pair while the data line pair D1-D1B are connected to SA1 through GD1-GD1B and GD2-GD2B pairs. This system has a unique S/N problem as described below. PA1 (4) A fourth problem has to do with coupling noise between global data lines. With the global data line twisting method shown in FIG. 23, an imbalance occurs in the coupling capacitance in the worst case and noise cannot be canceled out completely. PA1 (1) The semiconductor memory of this invention includes: a unit memory array having: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line separation switches; and sense amplifiers; PA1 wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by two serially connected global data line separation switches, and of two pairs of data lines arranged in the first direction, a first pair of data lines are connected through a data line connection switch to a connecting point between the global data line and the global data line separation switch and a second pair of data lines are connected through a data line connection switch to a connecting point between two global data line separation switches. PA1 (2) The semiconductor memory of this invention includes a unit memory array as defined in (1), PA1 wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one global data line separation switch, two pairs of data lines arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for two pairs of data lines arranged in the first direction are located on the opposing sides of the data lines. PA1 (3) The semiconductor memory of this invention includes a unit memory array as defined in (1), PA1 wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one global data line separation switch, two pairs of data lines arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for two pairs of data lines arranged in the first direction are located on the same sides of the data lines and shifted from each other in the second direction. PA1 (4) In the semiconductor memory described in (1) to (3), when reading data from two pairs of data lines arranged in the first direction or writing data into these data lines, a first data line connection switch between the first data line pair and the first global data line pair is turned on to connect the first data lines to a first sense amplifier, a second data line connection switch between the second data line pair and the second global data line pair is turned on to connect the second data lines to a second sense amplifier, and one or two global data line separation switches connected between the first global data line pair and the second global data line pair are turned off. PA1 (5) The semiconductor memory described in (1) to (3) further includes: column switches; column selection lines wired so that their longitudinal direction is set parallel to the second direction and used to control the column switches; a substrate; a first wiring layer; and a second wiring layer; wherein the column switches are formed on the substrate, the data lines are formed in the first wiring layer, the global data lines and the column selection lines are formed in the second wiring layer, the first wiring layer is interposed between the substrate and the second wiring layer, the global data lines are wired at a pitch of one global data line for every two data lines, and the column selection lines are wired at a pitch of one column selection line for every four or more data lines. PA1 (6) The semiconductor memory described in (1) to (3) further includes: column switches; column selection lines wired so that their longitudinal direction is set parallel to the second direction and used to control the column switches; a substrate; a first wiring layer; a second wiring layer; and a third wiring layer; wherein the column switches are formed on the substrate, the data lines are formed in the first wiring layer, the global data lines are formed in the second wiring layer, the column selection lines are formed in the third wiring layer, the distance from the substrate to the wiring layers increases in the order of the first wiring layer, the second wiring layer and the third wiring layer, the global data lines are wired at a pitch of one global data line for every two data lines, and the column selection lines are wired at a pitch of one column selection line for every four or more data lines. PA1 (7) The semiconductor memory of the present invention includes: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line separation switches; sense amplifiers; sense amplifier NMOS drive lines; sense amplifier PMOS drive lines; and a sense amplifier drive circuit; wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one or two global data line separation switches, the sense amplifier drive circuits comprise a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor, the first and second NMOS transistors have their sources connected to a first power supply and their drains connected to the sense amplifier NMOS drive line, the first and second PMOS transistors have their sources connected to a second power supply and their drains connected to the sense amplifier PMOS drive line, a current drive power of the first NMOS transistor is greater than that of the second NMOS transistor, and a current drive power of the first PMOS transistor is greater than that of the second PMOS transistor. PA1 (8) In the semiconductor memory described in (7), when loads of the sense amplifiers are large, the first NMOS transistor and the first PMOS transistor are turned on to connect the sense amplifier NMOS drive line to the first power supply and the sense amplifier PMOS drive line to the second power supply, and when loads of the sense amplifiers are small, the second NMOS transistor and the second PMOS transistor are turned on to connect the sense amplifier NMOS drive line to the first power supply and the sense amplifier PMOS drive line to the second power supply, in order to vary the current drive power of the sense amplifier drive circuit. PA1 (9) The semiconductor memory of this invention includes a unit memory array as defined in (1), wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one or two global data line separation switches, and when the sense amplifiers are activated after activating the word lines with the data line connection switches turned on, the resistance of the data line connection switches is increased. PA1 (10) In the semiconductor memory described in (1) to (9), the memory cell comprises one MOSFET as a switch and an information storing capacitor. PA1 (11) the semiconductor memory of this invention comprises: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line sense amplifiers; and data line sense amplifiers; and global data line separation switches; wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different global data line sense amplifiers, adjoining global data lines are connected to each other by the global data line separation switch, the data lines are connected to the data line sense amplifiers, the memory cell comprises one MOSFET as a switch and an information storing capacitor, the data line sense amplifier includes a MOSFET of the same conduction type as that of the memory cell MOSFET, and the global data line sense amplifier includes a MOSFET of a conduction type different from that of the memory cell MOSFET. PA1 (12) In the semiconductor memory described in (11), the data line sense amplifier has a current-to-voltage conversion function. PA1 (13) The semiconductor memory of this invention includes a unit memory array having: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line separation switches; and sense amplifiers; wherein two global data lines are parallelly arranged in close proximity of each other in the first direction to form a global data line pair; wherein two sets of a global data line separation switch or two sets of two global data line separation switches connected in series are arranged in the first direction to form a global data line separation switch pair; wherein a first global data line pair, a first global data line separation switch pair, a second global data line pair and a second global data line separation switch pair are arranged in the second direction in that order in close proximity of each other in order to form a first global data line group; wherein third and fourth global data line pairs are arranged in close proximity of the first and second global data line pairs in the first direction and third and fourth global data line separation switch pairs are arranged in close proximity of the first and second global data line separation switch pairs in the first direction in order to form a second global data line group; wherein the first and second global data line groups are combined to form a unit global data line group; wherein the unit global data line group is repetitively arranged in the first and second directions and additional global data line pairs are arranged in close proximity of those global data line separation switch pairs in the second direction which are located at the ends of these unit global data line groups with respect to the second direction, to form a memory array; PA1 wherein when connecting the global data line pairs arranged in their close proximity on both sides in the second direction, the first and fourth global data line separation switch pairs connect ends of those global data lines whose first direction positions are the same; wherein when connecting the global data line pairs arranged in their close proximity on both sides in the second direction, the second and third global data line separation switch pairs connect ends of those global data lines whose first direction positions are different; wherein if the global data line group arranged repetitively in the second direction is taken as a global data line column, the sense amplifiers are connected to at least two global data line pairs of each global data line column almost at the center of the global data lines. PA1 (14) The semiconductor memory of this invention includes a unit memory array as defined in (13), PA1 wherein the first to fourth global data line separation switch pairs, when connecting the global data line pairs arranged in close proximity on both sides thereof in the second direction, connect ends of those global data lines whose first direction positions are the same; wherein the second and third global data line pairs exchange their second direction positions at virtually the center of the global data lines and the first and fourth global data line pairs do not exchange their second direction positions; wherein if the global data line group arranged repetitively in the second direction is taken as a global data line column, the sense amplifiers are connected to at least two global data line pairs of each global data line column almost at the center of the global data lines. PA1 (15) In the semiconductor memory described in (13) or (14), of two data line pairs arranged in the first direction, a first data line pair is connected through a data line connection switch to a connecting point between the global data line and the global data line separation switch, and a second data line pair is connected through a data line connection switch to a connecting point between two global data line separation switches. PA1 (16) In the semiconductor memory described in (13) or (14), two data line pairs arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for the two data line pairs arranged in the first direction are located on the opposing sides of the data lines. PA1 (17) In the semiconductor memory described in (13) or (14), two data line pairs arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for the two data line pairs arranged in the first direction are located on the same sides of the data lines and shifted from each other in the second direction.
Suppose that the parasitic capacitance for each data line D is Cd, that the parasitic capacitance for a part of a global data line GD equal in length to D is Cgd and that the memory cell capacitance is Cs. The parasitic capacitance connected to an input GD0 to SA0 is Csa0(t)=Cs+Cd+Cgd, because the memory cell is connected. The parasitic capacitance connected to an input GD0B is Csa0(b)=Cd+Cgd, because the memory cell is not connected. Similarly, the parasitic capacitance connected to an input GD1 to SA1 is Csa1(t)=Cs+Cd+3Cgd and the parasitic capacitance connected to an input GD1B is Csa1(b)=Cd +3Cgd. Here, noise Vn(0) and Vn(1) induced by imbalance in memory capacitance between the input pairs for SA0 and SA1 are given as follows (as presented in "Ultra-LSI Memory" by Kyoo Itoh, Published by Baifukan, 1994, page 205): EQU Vn(0)=A.multidot.Cs.multidot.K0/(Cd+Cgd)! (1/2) (1) EQU Vn(1)=A.multidot.Cs.multidot.K1/(Cd+3Cgd)! (1/2) (2)
In these equations (1) and (2), A is a proportional constant, and K0 and K1 are amplification velocities for SA0 and SA1, respectively. When the parasitic capacitance for the global data line Cgd cannot be ignored, there is a possibility of Vn(0) increasing very greatly compared with Vn(1). This is because Cd+Cgd&lt;Cd+3Cgd and when SA0 and SA1 are driven with the same driving force, SA0 with a smaller parasitic capacitance is amplified faster, resulting in K0&gt;K1.
There is also a possibility that other noise or coupling noise from D0-D0B to D1-D1B may increase. This is because, if there is a difference in the amplification speed between SA0 and SA1, the D0-D0B pair is amplified rapidly to a large amplitude and the D1-D1B pair slowly so that the capacitance coupling noise to the D1-D1B pair whose signal is still small cannot be ignored.
Consider a case where, in FIG. 23, QM0 and QM5 are turned off and other global data line separation switches are turned on, which represents a worst case for sense amplifiers (SA) in SA1 and SB1 in which the read signal form the memory cell is the smallest. Suppose that under the condition that all global data lines are precharged to 1 V and floating, SA in SB1 is activated to amplify the sense amplifier node I1 to 2V and I1B to 0V. At this time, consider the coupling noise that global data lines connected to I3 and I3B receive. As to I3, GD9 receives a negative coupling from GD4B and GD6 receives a positive coupling from GD1. However, because the length of GD9 corresponds to that of 128 word lines and the length of GD6 to that of 256 word lines, the positive coupling is two times larger than the negative and thus the positive noise for 128 word lines remains intact. Next, as for I3B, GD8B receives a negative coupling from GD3B and GD7B receives a positive coupling from GD2. In this case, both GD8B and GD7B have the same length of 256 word lines and therefore the positive and negative couplings are canceled out. Because the noise differs between I3 and I3B, the operation margin for SA in SB3 deteriorates.
Conversely, let us consider the coupling noise that the global data lines connected to I1 and I1B receive when SA in SB3 is activated to amplify the sense amplifier node I3 to 2V and I3B to 0V. As to I1, GD2 receives a negative coupling from GD7B and GD1 receives a positive coupling from GD6. In this case, both GD2 and GD1 are 256 W long and their positive and negative couplings are canceled out. Next for I1B, GD4B receives a positive coupling from GD9 and GD3B receives a negative coupling from GD8B. Because GD4B is 128 W long and GD3B is 256 W long, the negative coupling is two times larger and thus the negative noise for the length of 128 W remains intact. Therefore, in this case, too, the noise differs between I1 and I1B, degrading the margin of operation of SA in SB1.
In a DRAM of a hierarchical data line structure, the object of the present invention is to (1) provide a circuit system which reduces the size of switches when forming data lines in hierarchical structures so that the chip area can be kept from increasing when the number of divisions of data lines is increased; (2) suppress increases in signal delay and power consumption in the global data lines; (3) offer an operation system that prevents deterioration of the S/N even when there is an imbalance in parasitic capacitance between global data lines; and (4) reduce the coupling noise between the global data lines.